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PI90LV211/PI90LVT211
1:6 Differential Clock Distribution Chip
Features
* * * * * * * Meets or Exceeds Requirements of ANSI TIA/EIA-644-1995 Designed for Clocking Rates up to 320MHz Operates from a single 3.3-V Supply Low-Voltage Differential Signaling (LVDS) with Output Voltages of 350mV into a 100-ohm load Choice between LVDS or TTL clock input Synchronous Enable/Disable Multiplexed clock input - Internal 300 kohm pullup resistor on all control pins - CLK and CLK have 110-ohm termination (PI90LVT211) Common and individual Enable/Disable control 50ps Output-to-Output Skew 24ps Period Jitter Bus Pins are High Impedance when disabled or with VCC <1.5V TTL Inputs are 5V Tolerant Power Dissipation at 300 MHz P190LV211 is functionally compatible with Motorola's (PECL) MC 10E211/MC100E211 >12kV ESD Protection Packaging (Pb-free & Green available): - 28-pin TSSOP (L) - 28-pin QSOP (Q)
Description
The PI90LV211 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320 MHz with low skew. The PI90LV211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The device features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock with the high-speed system clock. When LOW the SEL pin will select the differential clock input. Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative transition of the CLK (or SCLK) input. The enable function is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. Individual synchronous enable controls and multiplexed clock inputs make this device ideal as the first level distribution unit in a distribution tree. The individual enables could be used to allow for the disabling of individual cards on a backplane in fault tolerant designs.
* * * * * * * * *
Function Table
CLK/CLK H/L X SCLK X H/L SEL L H X H ENx L L H L CEN L L L H CLK OUT () CLK SCLK Z* Z**
Block Diagram & Pin Configuration
VCC EN1 1 2
D
28 27 26
VCC CLK1OUT+ CLK1OUT-
GND EN2 SCLK CLK
3 4
D
Q
25 24
Q
5 6
CLK2OUT+ CLK2OUT-
1
PI90LVT211 Only 110
* ENx disables individual banks ** CEN disables all six banks = Negative transition of CLK or SCLK Z = High Impedance
CLK EN3
7 8
D 0
23 22
Q
CLK3OUT+ CLK3OUT-
SEL
9
D
21 20
Q
CLK4OUT+ CLK4OUT-
EN4
10
D
19 18
Q
CLK5OUT+ CLK5OUT-
EN5 EN6
11 12
D
17 16
CLK6OUT+ CLK6OUT-
CEN GND
13 14
Q
15
GND
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted).
Symbol VOD VOD VOC(SS) VOC(SS) VOC(PP) ICC IIH IIL IOS IOZ IO(OFF) CIN CO RTERM Parame te r Differential output voltage magnitude Change in differential output voltage magnitude between logic states Steady- state common- mode output voltage Change in steady- state common- mode output voltage between logic states Peak- to- peak common- mode output voltage Supply Current High- level input current Low- level input current Short- circuit output current High- impedance output current Power- off output current Input capacitance, Output capacitance Termination Resistor Enabled, RL = 100 VIN = VCC or GND Disabled, VIN = VCC or GND VIH = 2V VIL = 0.8V VODOUT+ or VODOUT- = 0V VOD = 0V VO = 0V or VCC VCC = 1.1V, VO = 2.4V VI = 0.4 sin (4E6t) +0.5V VI = 0.4 sin (4E6t) +0.5V, Disabled PI90LVT211 90 9 10 110 132 See Figure 3 Te s t Conditions RL = 100 See Figures 1 and 2 M in. 247 -50 1.125 -50 40 27 3.0 4.8 9 1. 3 0 Typ.(1) 340 M ax. 454 50 1.60 50 mV 150 35 3.9 20 20 7 4.5 1 1 mA mV Units
V
A
mA
A
pF
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).
Characte ris tic Propagation De lay to Output CLK to CLKOUT SCLK to CLKOUT SEL to CLKOUT Dis able Time CLK or SCLK to CLKOUT Symbol tPLH tPHL M in. 1.5 1.5 1.5 Typ. 2.7 2.7 2.7 2.2 2.1 3.6 2.8 M a x. 3.4 3.24 3.6 ns tPHZ tPLZ tPZH tPZL tskew 2.8 2.8 4.8 4.8 TBD TBD TBD -48 -24 200 200 -100 0 600 0.20 0.125 150 1.5 400 140 25 30 250 760 0.800 VCC - 0.2 1200 180 60 100 MHz ps 5 6 7 V +48 +24 ps 2 Units Condition
Part-to-Part Ske w CLK (Diff) to Q CLK (SE), SCLK to Q With Device Skew Cycle -to-Cycle Jitte r Pe riod Jitte r Se tup Time ENx to CLK CEN to CLK Hold Time CLK to ENx, CEN M inimum Input Swing (CLK) Com. M ode Range (CLK) Ris e /Fall Time s 20 - 80% Duty Cycle Dis tortion Puls e Ske w ( tPLH - tPHL) SCLK to CLKOUT CLK to CLKOUT Channe l-to-Channe l Ske w, s ame e dge M aximum Ope rating Fre que ncy
1 Figure 6 Figure 7 2 2 3 4
tjit(cc) tjit(per) ts
th VPP VCMR tr, tf tSK1R tSK1R tSK2R
Notes: 1. Within-Device skew is defined for identical transitions on similar paths through a device. 2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK. 3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input swings. 4. The range in which the high level of the input swing must fall while meeting the VPP spec. 5. tSKIR is the difference in receiver propagation delay (tPLH-tPHL) of one device, and is the duty cycle distortion of the output at any given temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature. 6. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This parameter is guaranteed by design and characterization. 7. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak). Output Criteria: 60%/40% duty cycle, VOL (max) 0-4V, VOH (min) 2.7V, Load - 7pF (stray plus probes). 8. CL includes probe and fixture capacitance. 9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, ZO = 50 ohms, tr = 1ns, tf = 1ns (35%-65%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Parameter Measurement Information
IOY IOZ VOD DOUT- GND VODOUT+ VOC VODOUT-
II
DOUT+ DIN VI
(VODOUT++VODOUT-)/2
Figure 1. Voltage and Current Definitions
DOUT+ Input DOUT- VOD
3.75k 100 3.75k
0V VTEST 2.4V
Figure 2. VOD Test Circuit
3V DOUT+ 49.9 1% (2 places) Input DOUT-
VOC
VI
0V
VOC(PP) VOC(SS)
Figure 3. Test Circuit & Definitions for the Driver Common-Mode Output Voltage
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 50 Mpps, Pulse width = 10 0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T. Themeasurement of VOC(PP) is made on test equipment with a -3dB bandwidth of at least 300MHz.
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Parameter Measurement Information (continued)
32V 1.4V 0.8V
tPLH VOD 100 1% tPHL
Input DOUT+ Input DOUT-
CL= 10pF (2 places)
Output 0V
VOD(H) VOD(L)
100% 80% 20% 0%
tf
tr
Figure 4. Test Circuit, Timing, & Voltage Definitions for the Differential Output Signal
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 15 Mpps, Pulse width = 10 0.2ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
DOUT+ 0.8V or 2V DOUT- Input
49.9 1% (2 places)
VODOUT+ VODOUT-
+ 1.2V -
2V 1.4V Input 0.8V
tPZH VODOUT+
or
tPHZ 1.4V 1.3V 1.2V
VODOUT- tPZL VODOUT-
or
tPLZ 1.2V 1.1V 1V
VODOUT+
Figure 5. Enable & Disable Time Circuit & Definitions
Note: 1. All input pulses are supplied by a generator having the following characteristics: tr or tf 1ns, Pulse Repetition Rate (PRR) = 0.5 Mpps, Pulse width = 500 10ns. CL includes instrumentation and fixture capacitance within 0.06m of the D.U.T.
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
C L KO U T - C L KO U T +
t cycle n t jit(cc) = t cycle n - t cycle n+1
Figure 6. Cycle-to-Cycle Jitter
t cycle n+1
C L KO U T - C L KO U T +
t cycle n
C L KO U T - C L KO U T +
1 fO
t jit(per) = t cycle n
1 fO
Figure 7. Period Jitter
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BACKPLANE
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
General Desciption
The PI90LV211 is a 1:6 fanout tree designed explicitly for low-skew, high-speed clock distribution. The device was targeted to work in conjunction with the PI90LV14 device to provide another level of flexibility in the design and implementation of clock distribution trees. The individual synchronous enable controls and multiplexed clock inputs make the device ideal as the first level distribution unit in a distribution tree. The device provides the ability to distribute a lower speed scan or test clock along with the high-speed system clock to ease the design of system diagnostics and self test procedures. The individual enables could be used to allow for the disabling of individual cards on a backplane in fault tolerant designs. Handling Open Inputs and Outputs With the simultaneous switching characteristics and the tight skew specifications of the P90LV211, the handling of the unused outputs becomes critical. To minimize the noise generated on the die all outputs should be terminated in pairs, i.e. both the true and compliment outputs should be terminated even if only one of the outputs will be used in the system. With both complimentary pairs terminated, the current in the VCC pins will remain essentially constant and thus inductance induced voltage glitches on VCC will not occur. VCC glitches will result in distorted output waveforms and degradations in the skew performance of the device. The package parasitics of the 28-lead package cause the signals on a given pin to be influenced by signals on adjacent pins. PI90LV211 is characterized and tested with all of the outputs switching, therefore the numbers in the data book are guaranteed only for this situation. If all of the outputs of the PI90LV211 are not needed and there is a desire to save power, the unused output pairs can be left unterminated. Unterminated outputs can influence the propagation delay on adjacent pins by 15ps-20ps. Therefore, under these conditions, this 15ps-20ps needs to be added to the overall skew of the device. Pins which are separated by a package corner are not considered adjacent pins in the context of propagation delay influence. Therefore if all of the outputs on a single side of the package are terminated, the specification limits in the data sheet will apply. Using the Enable Pins Both the common enable (CEN) and the individual enables (ENx) are synchronous to the CLK or SCLK input depending on which is selected. The active low signals are clocked into the enable flip flops on the negative edges of the PI90LV211 clock inputs. In this way, the devices will only be disabled when the outputs are already in the LOW state. The internal propagation delays are such that the delay to the output through the distribution buffers is less than that through the enable flip flops. This will ensure that the disabling of the device will not slice any time off the clock pulse. On initial power up, the enable flip flops will randomly attain a stable state; therefore precautions should be taken on initial power up to ensure the PI90LV211 is in the desired state.
PI90LV14 PI90LV211
D0
PI90LV14
D5
Figure 8. Standard PI90LV211 LVDS Application
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Packaging Mechanical: 28-Pin TSSOP (L)
28
.169 .177
4.3 4.5
1 .378 .386 9.6 9.8 .047 1.20 Max SEATING PLANE 0.45 0.75 .018 .030
.004 .008
0.09 0.20
.252 BSC 6.4
X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
Packaging Mechanical: 28-Pin QSOP (Q)
28
.008 0.20 MIN.
0.150 0.157
3.81 3.99
Guage Plane
.008 .013 0.20 0.33
.010 0.254
1 .386 9.804 .394 10.009
Detail A
.016 .035 0.41 0.89
.041 1.04 REF
0-6
.033 REF 0.84
1.35 .053 1.75 .069 SEATING PLANE
.015 x 45
Detail A
.007 0.178 .010 0.254 0.41 .016 1.27 .050 .228 .244 5.79 6.19
.025 BSC 0.635
.008 0.203 .012 0.305
.004 0.101 .010 0.254
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
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PI90LV211/PI90LVT211 1:6 Differential Clock Distribution Chip
Ordering Information
Ordering Code PI90LV211L PI90LV211LE PI90LV211Q PI90LV211QE PI90LVT211L PI90LVT211LE PI90LVT211Q PI90LVT211QE Package Code L L Q Q L L Q Q Package Type 28-pin 173-mil TSSOP Pb-free & Green, 28-pin 173-mil TSSOP 28-pin 150-mil QSOP Pb-free & Green, 28-pin 150-mil QSOP 28-pin 173-mil TSSOP Pb-free & Green, 28-pin 173-mil TSSOP 28-pin 150-mil QSOP Pb-free & Green, 28-pin 150-mil QSOP
Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
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